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0x0E - IRQCFG0E [default 0x01]
Name
Bits
R/W
Description
FIFO fill mode selection:
Start_Fill
7
r/w
0 → FIFO starts filling when start pattern is recognized
1 → FIFO fills as long as Start_Det is 1
Start of FIFO fill:
If Start_Fill = 0, goes high when start pattern recognized. Write a 1 to reset the start pattern
Start_Det
6
r/w/c
recognition.
If Start_Fill = 1
0 → Stop filling FIFO
1 → Start filling FIFO
Transmit state:
TX_Stop
5
r
0 → Transferring bits to the TX modulator
1 → Last bit transferred to the TX modulator
FIFO overflow:
FIFO_OVR
4
r/w/c
In Buffered data mode, writing a 1 to this bit clears the FIFO.
In Packet data mode, writing a 1 to this bit clears the FIFO and allows a new packet to be transmitted
or received immediately.
Enables SIG_DETECT when RSSI_thld is tripped:
RSSI_Int
3
r/w
0 → Disable interrupt
1→ Enable interrupt
Detects a signal above the RSSI_thld:
SIG_DETECT
2
r/w/c
0 → Signal lower than threshold
1 → Signal equal or greater than the RSSI_thld level
This bit latches high and must be cleared by writing a 1 to its location.
Detects the PLL lock status:
PLL_LOCK_ST
1
r/w/c
0 → PLL not locked
1 → PLL locked
This bit latches high each time the PLL locks and must be cleared by writing a 1 to its location.
Enables the PLL_LOCK signal on Pin 23
PLL_LOCK_EN
0
r/w
0 → PLL_LOCK signal disabled, Pin 23 set high
1 → PLL_LOCK signal enabled
Table 29
0x0F - IRQCFG0F [default 0x00]
Name
RSSI_thld(7..0)
Bits
7..0
R/W
r/w
Description
RSSI threshold level for interrupt.
RSSI_thld default is 0x00
Table 30
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TRC105 - 05/29/13
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